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[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_immu_top.v] - Rev 1773

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Rev Log message Author Age Path
1765 root 5716d 15h /or1k/trunk/or1200/rtl/verilog/or1200_immu_top.v
1293 Non-functional changes. Coding style fixes. lampret 7452d 20h /or1k/trunk/or1200/rtl/verilog/or1200_immu_top.v
1267 Merged branch_qmem into main tree. lampret 7517d 06h /or1k/trunk/or1200/rtl/verilog/or1200_immu_top.v
1200 mbist signals updated according to newest convention markom 7688d 06h /or1k/trunk/or1200/rtl/verilog/or1200_immu_top.v
1161 When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed. lampret 7821d 11h /or1k/trunk/or1200/rtl/verilog/or1200_immu_top.v
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 8052d 18h /or1k/trunk/or1200/rtl/verilog/or1200_immu_top.v
1053 Disabled cache inhibit atttribute. lampret 8084d 11h /or1k/trunk/or1200/rtl/verilog/or1200_immu_top.v
977 Added store buffer. lampret 8112d 18h /or1k/trunk/or1200/rtl/verilog/or1200_immu_top.v
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 8117d 08h /or1k/trunk/or1200/rtl/verilog/or1200_immu_top.v
942 Delayed external access at page crossing. lampret 8119d 09h /or1k/trunk/or1200/rtl/verilog/or1200_immu_top.v
788 Some of the warnings fixed. lampret 8254d 23h /or1k/trunk/or1200/rtl/verilog/or1200_immu_top.v
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8301d 10h /or1k/trunk/or1200/rtl/verilog/or1200_immu_top.v
636 Fixed combinational loops. lampret 8310d 18h /or1k/trunk/or1200/rtl/verilog/or1200_immu_top.v
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8315d 13h /or1k/trunk/or1200/rtl/verilog/or1200_immu_top.v
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8329d 08h /or1k/trunk/or1200/rtl/verilog/or1200_immu_top.v
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8340d 06h /or1k/trunk/or1200/rtl/verilog/or1200_immu_top.v

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