URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_rfram_generic.v] - Rev 1781

Rev	Log message	Author	Age	Path
1765		root	5744d 06h	/or1k/trunk/or1200/rtl/verilog/or1200_rfram_generic.v
1292	GPR0 hardwired to zero.	lampret	7480d 11h	/or1k/trunk/or1200/rtl/verilog/or1200_rfram_generic.v
1022	As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.	lampret	8124d 06h	/or1k/trunk/or1200/rtl/verilog/or1200_rfram_generic.v
871	Generic flip-flop based memory macro for register file.	lampret	8211d 13h	/or1k/trunk/or1200/rtl/verilog/or1200_rfram_generic.v