URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_2048x32.v] - Rev 1774

Rev	Log message	Author	Age	Path
1765		root	5628d 16h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_2048x32.v
1582	Added support for RAMB16 Xilinx4/Spartan3 primitives	jcastillo	6867d 03h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_2048x32.v
1291	Changed behavior of the simulation generic models	lampret	7364d 20h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_2048x32.v
1267	Merged branch_qmem into main tree.	lampret	7429d 06h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_2048x32.v
1200	mbist signals updated according to newest convention	markom	7600d 06h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_2048x32.v
1184	Scan signals mess fixed.	simons	7658d 22h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_2048x32.v
1179	BIST interface added for Artisan memory instances.	simons	7667d 01h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_2048x32.v
1129	Added Altera LPM RAMs. Changed generic RAM output when OE inactive.	lampret	7793d 13h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_2048x32.v
1077	Signal scanb_sen renamed to scanb_en.	mohor	7953d 23h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_2048x32.v
1063	Added BIST scan. Special VS RAMs need to be used to implement BIST.	lampret	7964d 18h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_2048x32.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8252d 06h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_2048x32.v