URL https://opencores.org/ocsvn/or1k/or1k/trunk

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[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_2048x32_bw.v] - Rev 1765

Rev	Log message	Author	Age	Path
1765		root	5741d 16h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
1582	Added support for RAMB16 Xilinx4/Spartan3 primitives	jcastillo	6980d 03h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
1291	Changed behavior of the simulation generic models	lampret	7477d 20h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
1200	mbist signals updated according to newest convention	markom	7713d 06h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
1194	correct all the syntax errors	dries	7748d 05h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
1186	Added support for rams with byte write access.	simons	7765d 05h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_2048x32_bw.v