URL https://opencores.org/ocsvn/or1k/or1k/trunk

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[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_32x24.v] - Rev 1774

Rev	Log message	Author	Age	Path
1765		root	5628d 16h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_32x24.v
1582	Added support for RAMB16 Xilinx4/Spartan3 primitives	jcastillo	6867d 03h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_32x24.v
1291	Changed behavior of the simulation generic models	lampret	7364d 20h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_32x24.v
1273	Add support for 512B instruction cache.	simont	7426d 03h	/or1k/trunk/or1200/rtl/verilog/or1200_spram_32x24.v