OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_sprs.v] - Rev 1774

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5601d 19h /or1k/trunk/or1200/rtl/verilog/or1200_sprs.v
1267 Merged branch_qmem into main tree. lampret 7402d 10h /or1k/trunk/or1200/rtl/verilog/or1200_sprs.v
1207 Static exception prefix. lampret 7524d 18h /or1k/trunk/or1200/rtl/verilog/or1200_sprs.v
1032 Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. lampret 7978d 12h /or1k/trunk/or1200/rtl/verilog/or1200_sprs.v
1011 Removed some commented RTL. Fixed SR/ESR flag bug. lampret 7988d 16h /or1k/trunk/or1200/rtl/verilog/or1200_sprs.v
788 Some of the warnings fixed. lampret 8140d 03h /or1k/trunk/or1200/rtl/verilog/or1200_sprs.v
736 Changed generation of SPR address. Now it is ORed from base and offset instead of a sum. lampret 8158d 17h /or1k/trunk/or1200/rtl/verilog/or1200_sprs.v
636 Fixed combinational loops. lampret 8195d 22h /or1k/trunk/or1200/rtl/verilog/or1200_sprs.v
610 Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. lampret 8205d 10h /or1k/trunk/or1200/rtl/verilog/or1200_sprs.v
596 SR[TEE] should be zero after reset. lampret 8209d 09h /or1k/trunk/or1200/rtl/verilog/or1200_sprs.v
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8210d 10h /or1k/trunk/or1200/rtl/verilog/or1200_sprs.v
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8225d 10h /or1k/trunk/or1200/rtl/verilog/or1200_sprs.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.