URL https://opencores.org/ocsvn/or1k/or1k/trunk

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[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_tpram_32x32.v] - Rev 1765

Rev	Log message	Author	Age	Path
1765		root	5732d 01h	/or1k/trunk/or1200/rtl/verilog/or1200_tpram_32x32.v
1582	Added support for RAMB16 Xilinx4/Spartan3 primitives	jcastillo	6970d 12h	/or1k/trunk/or1200/rtl/verilog/or1200_tpram_32x32.v
1291	Changed behavior of the simulation generic models	lampret	7468d 05h	/or1k/trunk/or1200/rtl/verilog/or1200_tpram_32x32.v
1267	Merged branch_qmem into main tree.	lampret	7532d 15h	/or1k/trunk/or1200/rtl/verilog/or1200_tpram_32x32.v
1129	Added Altera LPM RAMs. Changed generic RAM output when OE inactive.	lampret	7896d 22h	/or1k/trunk/or1200/rtl/verilog/or1200_tpram_32x32.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8355d 15h	/or1k/trunk/or1200/rtl/verilog/or1200_tpram_32x32.v