OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [or1ksim/] [peripheral/] [atahost.h] - Rev 1773

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5731d 14h /or1k/trunk/or1ksim/peripheral/atahost.h
1748 These are all the changes for Or1ksim 0.3.0 release candidate 1. The changes
are explained in the NEWS, README and ChangeLog files. A number of
long-standing bugs are fixed (see the OpenRISC tracker), and the code is
brought up to a consistent standard, following the GNU coding conventions
throughout.

Argument parsing now uses argtable2, and a User Guide has been added.
Documentation throughout has been extended to be compatible with Doxygen,
providing a further level of technical detail on the internals.
jeremybennett 5880d 19h /or1k/trunk/or1ksim/peripheral/atahost.h
1726 Generate an interrupt when it is time to do so. nogj 6877d 16h /or1k/trunk/or1ksim/peripheral/atahost.h
1702 Make the default pio and dma settings be configurable from the config file. nogj 6877d 16h /or1k/trunk/or1ksim/peripheral/atahost.h
1701 Make the OCIDEC type and revision settable via the config file. nogj 6877d 16h /or1k/trunk/or1ksim/peripheral/atahost.h
1698 Use proper types. nogj 6877d 16h /or1k/trunk/or1ksim/peripheral/atahost.h
1649 Mark as many functions as possible static nogj 6877d 18h /or1k/trunk/or1ksim/peripheral/atahost.h
1486 * Seporate out the code used for handling the memory peripheral to peripheral/memory.c
* Mostly decouple the memory controller from the internals of the memory handling.
* Rewrite memory handling to be more linear and thus much faster.
* Issue a bus error on read/write with invalid granularity.
nogj 7124d 02h /or1k/trunk/or1ksim/peripheral/atahost.h
1461 Add an optional `enabled' paramter to every peripheral nogj 7171d 21h /or1k/trunk/or1ksim/peripheral/atahost.h
1364 Clean up the ata peripheral useing the new set of callbacks nogj 7212d 16h /or1k/trunk/or1ksim/peripheral/atahost.h
1359 Pass private data in readfunc/writefunc callbacks nogj 7212d 16h /or1k/trunk/or1ksim/peripheral/atahost.h
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7221d 19h /or1k/trunk/or1ksim/peripheral/atahost.h
1308 Gyorgy Jeney: extensive cleanup phoenix 7426d 14h /or1k/trunk/or1ksim/peripheral/atahost.h
919 stable release rherveille 8145d 19h /or1k/trunk/or1ksim/peripheral/atahost.h
876 Beta release of ATA simulation rherveille 8174d 14h /or1k/trunk/or1ksim/peripheral/atahost.h

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.