OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [or1ksim/] [peripheral/] [eth.c] - Rev 1780

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5561d 19h /or1k/trunk/or1ksim/peripheral/eth.c
1751 These are the changes to support Or1ksim 0.3.0rc2. Most significantly they provide GDB RSP support. They also fix 5 outstanding bugs and satisfy one new feature request. jeremybennett 5681d 04h /or1k/trunk/or1ksim/peripheral/eth.c
1748 These are all the changes for Or1ksim 0.3.0 release candidate 1. The changes
are explained in the NEWS, README and ChangeLog files. A number of
long-standing bugs are fixed (see the OpenRISC tracker), and the code is
brought up to a consistent standard, following the GNU coding conventions
throughout.

Argument parsing now uses argtable2, and a User Guide has been added.
Documentation throughout has been extended to be compatible with Doxygen,
providing a further level of technical detail on the internals.
jeremybennett 5711d 00h /or1k/trunk/or1ksim/peripheral/eth.c
1715 Add the capability to the pic to simulate a level or edge triggered pic. Add
a clear_interrupt() function that the peripherals need to use to signal that
they negated their interrupt line.
nogj 6707d 21h /or1k/trunk/or1ksim/peripheral/eth.c
1649 Mark as many functions as possible static nogj 6707d 22h /or1k/trunk/or1ksim/peripheral/eth.c
1606 fix uninitialized reads phoenix 6763d 04h /or1k/trunk/or1ksim/peripheral/eth.c
1598 Handle ethernet addresses as an address and not as an int nogj 6782d 01h /or1k/trunk/or1ksim/peripheral/eth.c
1557 Fix most warnings issued by gcc4 nogj 6844d 09h /or1k/trunk/or1ksim/peripheral/eth.c
1487 Remove useless *breakpoint argument from the {set,eval}_direct* functions nogj 6949d 10h /or1k/trunk/or1ksim/peripheral/eth.c
1486 * Seporate out the code used for handling the memory peripheral to peripheral/memory.c
* Mostly decouple the memory controller from the internals of the memory handling.
* Rewrite memory handling to be more linear and thus much faster.
* Issue a bus error on read/write with invalid granularity.
nogj 6954d 06h /or1k/trunk/or1ksim/peripheral/eth.c
1469 Don't halt the sim when not needed nogj 7002d 01h /or1k/trunk/or1ksim/peripheral/eth.c
1463 Make the ethernet peripheral use the new debug channels nogj 7002d 01h /or1k/trunk/or1ksim/peripheral/eth.c
1461 Add an optional `enabled' paramter to every peripheral nogj 7002d 01h /or1k/trunk/or1ksim/peripheral/eth.c
1390 * Change scheduler to count down to 0 instead of reaching a certain cycle
count.
* Change the SCHED_ADD interface to take a time out as the parameter instead of the number of cycles.
nogj 7002d 02h /or1k/trunk/or1ksim/peripheral/eth.c
1388 Remove useless define nogj 7008d 05h /or1k/trunk/or1ksim/peripheral/eth.c
1372 Cleanup ethernet peripheral, useing the new callbacks nogj 7042d 20h /or1k/trunk/or1ksim/peripheral/eth.c
1366 Pass a caller given pointer to the vapi_read callback nogj 7042d 20h /or1k/trunk/or1ksim/peripheral/eth.c
1359 Pass private data in readfunc/writefunc callbacks nogj 7042d 21h /or1k/trunk/or1ksim/peripheral/eth.c
1358 Modularise config file parseing. Paving the way for further modularisation. nogj 7042d 21h /or1k/trunk/or1ksim/peripheral/eth.c
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7052d 00h /or1k/trunk/or1ksim/peripheral/eth.c

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.