OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [or1ksim/] [sim.cfg] - Rev 1775

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5744d 06h /or1k/trunk/or1ksim/sim.cfg
1748 These are all the changes for Or1ksim 0.3.0 release candidate 1. The changes
are explained in the NEWS, README and ChangeLog files. A number of
long-standing bugs are fixed (see the OpenRISC tracker), and the code is
brought up to a consistent standard, following the GNU coding conventions
throughout.

Argument parsing now uses argtable2, and a User Guide has been added.
Documentation throughout has been extended to be compatible with Doxygen,
providing a further level of technical detail on the internals.
jeremybennett 5893d 11h /or1k/trunk/or1ksim/sim.cfg
1715 Add the capability to the pic to simulate a level or edge triggered pic. Add
a clear_interrupt() function that the peripherals need to use to signal that
they negated their interrupt line.
nogj 6890d 08h /or1k/trunk/or1ksim/sim.cfg
1712 Make heads/sectors/firmware date/supported pio/mwdma modes be configureable from
the config file
nogj 6890d 08h /or1k/trunk/or1ksim/sim.cfg
1703 Introduce a device sub-section into the ata section and avoid confuseing
xx{0,1} parameters
nogj 6890d 08h /or1k/trunk/or1ksim/sim.cfg
1702 Make the default pio and dma settings be configurable from the config file. nogj 6890d 08h /or1k/trunk/or1ksim/sim.cfg
1701 Make the OCIDEC type and revision settable via the config file. nogj 6890d 08h /or1k/trunk/or1ksim/sim.cfg
1700 The ata section of the config file does not have the debug keywork anymore.
Remove it.
nogj 6890d 08h /or1k/trunk/or1ksim/sim.cfg
1537 Remove old spr logging code. Use `-d +spr' to get spr access logged to stderr nogj 7088d 22h /or1k/trunk/or1ksim/sim.cfg
1486 * Seporate out the code used for handling the memory peripheral to peripheral/memory.c
* Mostly decouple the memory controller from the internals of the memory handling.
* Rewrite memory handling to be more linear and thus much faster.
* Issue a bus error on read/write with invalid granularity.
nogj 7136d 17h /or1k/trunk/or1ksim/sim.cfg
1461 Add an optional `enabled' paramter to every peripheral nogj 7184d 12h /or1k/trunk/or1ksim/sim.cfg
1374 Cleanup the gpio peripheral useing the new callbacks nogj 7225d 07h /or1k/trunk/or1ksim/sim.cfg
1372 Cleanup ethernet peripheral, useing the new callbacks nogj 7225d 07h /or1k/trunk/or1ksim/sim.cfg
1371 Cleanup kbd peripheral useing the new callbacks nogj 7225d 07h /or1k/trunk/or1ksim/sim.cfg
1370 Cleanup dma peripheral useing the new callbacks nogj 7225d 07h /or1k/trunk/or1ksim/sim.cfg
1369 Cleanup FB peripheral, useing the new callbacks nogj 7225d 07h /or1k/trunk/or1ksim/sim.cfg
1368 Cleanup VGA peripheral useing the new callbacks nogj 7225d 07h /or1k/trunk/or1ksim/sim.cfg
1367 Cleanup uart peripheral useing the new callback mechanism nogj 7225d 07h /or1k/trunk/or1ksim/sim.cfg
1364 Clean up the ata peripheral useing the new set of callbacks nogj 7225d 07h /or1k/trunk/or1ksim/sim.cfg
1126 Added lengthy comment explaining all possible choices for UART
channels, e.g. xterm, tcp, file, etc.
sfurman 7919d 05h /or1k/trunk/or1ksim/sim.cfg

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.