URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [or1ksim/] [testbench/] [cache.c] - Rev 1767

Rev	Log message	Author	Age	Path
1765		root	5730d 13h	/or1k/trunk/or1ksim/testbench/cache.c
631	Real cache access is simulated now.	simons	8327d 14h	/or1k/trunk/or1ksim/testbench/cache.c
621	Cache test works on hardware.	simons	8329d 01h	/or1k/trunk/or1ksim/testbench/cache.c
575	Not needed to be compiled with -O2 optimization any more.	simons	8342d 00h	/or1k/trunk/or1ksim/testbench/cache.c
574	fixed some tests to work	markom	8342d 02h	/or1k/trunk/or1ksim/testbench/cache.c
534	Changed to work with new simulator.	simons	8349d 23h	/or1k/trunk/or1ksim/testbench/cache.c
484	Changed to support execution from various addresses.	simons	8368d 17h	/or1k/trunk/or1ksim/testbench/cache.c
424	memory configuration file joined into .cfg file; *mem.cfg are obsolete; read-only and write-only memory is supported; memory logging is not yet supported; update of testbench - only cache test fails, since it writes to RO memory	markom	8377d 01h	/or1k/trunk/or1ksim/testbench/cache.c
349	Some bugs regarding cache simulation fixed.	simons	8401d 16h	/or1k/trunk/or1ksim/testbench/cache.c
322	IC test repaired.C	simons	8407d 18h	/or1k/trunk/or1ksim/testbench/cache.c
224	added various tests	markom	8425d 00h	/or1k/trunk/or1ksim/testbench/cache.c