URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

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[/] [or1k_old/] [branches/] [branch_speed_opt/] [or1200/] [rtl/] [verilog/] [or1200_ic_ram.v] - Rev 1782

Rev	Log message	Author	Age	Path
1782		root	5797d 00h	/or1k_old/branches/branch_speed_opt/or1200/rtl/verilog/or1200_ic_ram.v
1765		root	5907d 16h	/or1k_old/branches/branch_speed_opt/or1200/rtl/verilog/or1200_ic_ram.v
1164	This commit was manufactured by cvs2svn to create branch 'branch_speed_opt'.		8012d 12h	/or1k_old/branches/branch_speed_opt/or1200/rtl/verilog/or1200_ic_ram.v
1063	Added BIST scan. Special VS RAMs need to be used to implement BIST.	lampret	8243d 19h	/or1k_old/branches/branch_speed_opt/or1200/rtl/verilog/or1200_ic_ram.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8531d 07h	/or1k_old/branches/branch_speed_opt/or1200/rtl/verilog/or1200_ic_ram.v