URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] [or1k_old/] [branches/] [branch_speed_opt/] [or1200/] [rtl/] [verilog/] [or1200_mult_mac.v] - Rev 1782

Rev	Log message	Author	Age	Path
1782		root	5794d 19h	/or1k_old/branches/branch_speed_opt/or1200/rtl/verilog/or1200_mult_mac.v
1765		root	5905d 11h	/or1k_old/branches/branch_speed_opt/or1200/rtl/verilog/or1200_mult_mac.v
1164	This commit was manufactured by cvs2svn to create branch 'branch_speed_opt'.		8010d 07h	/or1k_old/branches/branch_speed_opt/or1200/rtl/verilog/or1200_mult_mac.v
1159	No functional changes. Added defines to disable implementation of multiplier/MAC	lampret	8053d 10h	/or1k_old/branches/branch_speed_opt/or1200/rtl/verilog/or1200_mult_mac.v
1035	Added optional l.div/l.divu insns. By default they are disabled.	lampret	8281d 04h	/or1k_old/branches/branch_speed_opt/or1200/rtl/verilog/or1200_mult_mac.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8529d 02h	/or1k_old/branches/branch_speed_opt/or1200/rtl/verilog/or1200_mult_mac.v