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[/] [or1k_old/] [tags/] [nog_patch_64/] [or1ksim/] [cache/] [dcache_model.h] - Rev 1782

Rev	Log message	Author	Age	Path
1782		root	5515d 13h	/or1k_old/tags/nog_patch_64/or1ksim/cache/dcache_model.h
1765		root	5626d 05h	/or1k_old/tags/nog_patch_64/or1ksim/cache/dcache_model.h
1454	This commit was manufactured by cvs2svn to create tag 'nog_patch_64'.		7066d 11h	/or1k_old/tags/nog_patch_64/or1ksim/cache/dcache_model.h
1402	Do what dc_clock() did in mtspr() and remove it	nogj	7066d 12h	/or1k_old/tags/nog_patch_64/or1ksim/cache/dcache_model.h
1382	Nir Mor: Implemented DCCFGR, ICCFGR, DMMUCFGR and IMMUCFGR spr registers.	nogj	7081d 15h	/or1k_old/tags/nog_patch_64/or1ksim/cache/dcache_model.h
1350	Mark a simulated cpu address as such, by introducing the new oraddr_t type	nogj	7116d 10h	/or1k_old/tags/nog_patch_64/or1ksim/cache/dcache_model.h
1308	Gyorgy Jeney: extensive cleanup	phoenix	7321d 04h	/or1k_old/tags/nog_patch_64/or1ksim/cache/dcache_model.h
631	Real cache access is simulated now.	simons	8223d 05h	/or1k_old/tags/nog_patch_64/or1ksim/cache/dcache_model.h
626	store buffer added	markom	8223d 18h	/or1k_old/tags/nog_patch_64/or1ksim/cache/dcache_model.h
428	cache configuration added	markom	8272d 13h	/or1k_old/tags/nog_patch_64/or1ksim/cache/dcache_model.h
5	Data and instruction cache simulation added.	lampret	8921d 06h	/or1k_old/tags/nog_patch_64/or1ksim/cache/dcache_model.h