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[/] [or1k_old/] [tags/] [nog_patch_64/] [or1ksim/] [cache/] [icache_model.h] - Rev 1782

Rev	Log message	Author	Age	Path
1782		root	5489d 23h	/or1k_old/tags/nog_patch_64/or1ksim/cache/icache_model.h
1765		root	5600d 15h	/or1k_old/tags/nog_patch_64/or1ksim/cache/icache_model.h
1454	This commit was manufactured by cvs2svn to create tag 'nog_patch_64'.		7040d 22h	/or1k_old/tags/nog_patch_64/or1ksim/cache/icache_model.h
1404	Move the function of ic_clock() to mtspr() and remove it	nogj	7040d 22h	/or1k_old/tags/nog_patch_64/or1ksim/cache/icache_model.h
1382	Nir Mor: Implemented DCCFGR, ICCFGR, DMMUCFGR and IMMUCFGR spr registers.	nogj	7056d 02h	/or1k_old/tags/nog_patch_64/or1ksim/cache/icache_model.h
1350	Mark a simulated cpu address as such, by introducing the new oraddr_t type	nogj	7090d 20h	/or1k_old/tags/nog_patch_64/or1ksim/cache/icache_model.h
1308	Gyorgy Jeney: extensive cleanup	phoenix	7295d 15h	/or1k_old/tags/nog_patch_64/or1ksim/cache/icache_model.h
631	Real cache access is simulated now.	simons	8197d 16h	/or1k_old/tags/nog_patch_64/or1ksim/cache/icache_model.h
429	cache configuration added	markom	8246d 23h	/or1k_old/tags/nog_patch_64/or1ksim/cache/icache_model.h
102	Major update to include PM, PIC, Cache Mngmnt and non-interactive mode.	lampret	8454d 09h	/or1k_old/tags/nog_patch_64/or1ksim/cache/icache_model.h
76	regular update	lampret	8654d 07h	/or1k_old/tags/nog_patch_64/or1ksim/cache/icache_model.h
5	Data and instruction cache simulation added.	lampret	8895d 17h	/or1k_old/tags/nog_patch_64/or1ksim/cache/icache_model.h