URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

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[/] [or1k_old/] [tags/] [rel_13/] [or1200/] [rtl/] [verilog/] [or1200_wb_biu.v] - Rev 1782

Rev	Log message	Author	Age	Path
1782		root	5551d 10h	/or1k_old/tags/rel_13/or1200/rtl/verilog/or1200_wb_biu.v
1765		root	5662d 02h	/or1k_old/tags/rel_13/or1200/rtl/verilog/or1200_wb_biu.v
1189	This commit was manufactured by cvs2svn to create tag 'rel_13'.		7684d 16h	/or1k_old/tags/rel_13/or1200/rtl/verilog/or1200_wb_biu.v
1140	Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs.	lampret	7826d 04h	/or1k_old/tags/rel_13/or1200/rtl/verilog/or1200_wb_biu.v
1104	Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.	lampret	7946d 16h	/or1k_old/tags/rel_13/or1200/rtl/verilog/or1200_wb_biu.v
1054	Fixed a combinational loop.	lampret	8029d 22h	/or1k_old/tags/rel_13/or1200/rtl/verilog/or1200_wb_biu.v
943	Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers.	lampret	8064d 19h	/or1k_old/tags/rel_13/or1200/rtl/verilog/or1200_wb_biu.v
895	Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.	lampret	8093d 03h	/or1k_old/tags/rel_13/or1200/rtl/verilog/or1200_wb_biu.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8285d 17h	/or1k_old/tags/rel_13/or1200/rtl/verilog/or1200_wb_biu.v