URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] [or1k_old/] [tags/] [rel_22/] [or1200/] [rtl/] [verilog/] [or1200_spram_1024x8.v] - Rev 1782

Rev	Log message	Author	Age	Path
1782		root	5551d 10h	/or1k_old/tags/rel_22/or1200/rtl/verilog/or1200_spram_1024x8.v
1765		root	5662d 02h	/or1k_old/tags/rel_22/or1200/rtl/verilog/or1200_spram_1024x8.v
1232	This commit was manufactured by cvs2svn to create tag 'rel_22'.		7541d 05h	/or1k_old/tags/rel_22/or1200/rtl/verilog/or1200_spram_1024x8.v
1214	Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.	simons	7580d 13h	/or1k_old/tags/rel_22/or1200/rtl/verilog/or1200_spram_1024x8.v
1163	This commit was manufactured by cvs2svn to create branch 'branch_qmem'.		7766d 21h	/or1k_old/tags/rel_22/or1200/rtl/verilog/or1200_spram_1024x8.v
1129	Added Altera LPM RAMs. Changed generic RAM output when OE inactive.	lampret	7826d 23h	/or1k_old/tags/rel_22/or1200/rtl/verilog/or1200_spram_1024x8.v
1063	Added BIST scan. Special VS RAMs need to be used to implement BIST.	lampret	7998d 04h	/or1k_old/tags/rel_22/or1200/rtl/verilog/or1200_spram_1024x8.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8285d 16h	/or1k_old/tags/rel_22/or1200/rtl/verilog/or1200_spram_1024x8.v