URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

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[/] [or1k_old/] [tags/] [rel_22/] [or1200/] [rtl/] [verilog/] [or1200_spram_64x24.v] - Rev 1782

Rev	Log message	Author	Age	Path
1782		root	5514d 12h	/or1k_old/tags/rel_22/or1200/rtl/verilog/or1200_spram_64x24.v
1765		root	5625d 04h	/or1k_old/tags/rel_22/or1200/rtl/verilog/or1200_spram_64x24.v
1232	This commit was manufactured by cvs2svn to create tag 'rel_22'.		7504d 08h	/or1k_old/tags/rel_22/or1200/rtl/verilog/or1200_spram_64x24.v
1214	Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.	simons	7543d 15h	/or1k_old/tags/rel_22/or1200/rtl/verilog/or1200_spram_64x24.v
1163	This commit was manufactured by cvs2svn to create branch 'branch_qmem'.		7730d 00h	/or1k_old/tags/rel_22/or1200/rtl/verilog/or1200_spram_64x24.v
1129	Added Altera LPM RAMs. Changed generic RAM output when OE inactive.	lampret	7790d 02h	/or1k_old/tags/rel_22/or1200/rtl/verilog/or1200_spram_64x24.v
1063	Added BIST scan. Special VS RAMs need to be used to implement BIST.	lampret	7961d 07h	/or1k_old/tags/rel_22/or1200/rtl/verilog/or1200_spram_64x24.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8248d 19h	/or1k_old/tags/rel_22/or1200/rtl/verilog/or1200_spram_64x24.v