URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [mp3/] [bench/] [verilog/] [or1200_monitor.v] - Rev 1782

Rev	Log message	Author	Age	Path
1782		root	5510d 00h	/or1k_old/trunk/mp3/bench/verilog/or1200_monitor.v
1765		root	5620d 16h	/or1k_old/trunk/mp3/bench/verilog/or1200_monitor.v
636	Fixed combinational loops.	lampret	8214d 19h	/or1k_old/trunk/mp3/bench/verilog/or1200_monitor.v
618	Fixed display of new 'void' nop insns.	lampret	8219d 13h	/or1k_old/trunk/mp3/bench/verilog/or1200_monitor.v
597	Fixed OR1200_XILINX_RAM32X1D.	lampret	8228d 01h	/or1k_old/trunk/mp3/bench/verilog/or1200_monitor.v
591	Added support for reading XILINX_RAM32X1D register file.	lampret	8229d 07h	/or1k_old/trunk/mp3/bench/verilog/or1200_monitor.v
563	Added debug model for testing du. Updated or1200_monitor.	lampret	8233d 08h	/or1k_old/trunk/mp3/bench/verilog/or1200_monitor.v
506	Added second clock as RISC main clock. Updated or120_monitor.	lampret	8244d 06h	/or1k_old/trunk/mp3/bench/verilog/or1200_monitor.v
368	Typos.	lampret	8285d 06h	/or1k_old/trunk/mp3/bench/verilog/or1200_monitor.v
318	Modified monitor tu support exceptions.	lampret	8298d 10h	/or1k_old/trunk/mp3/bench/verilog/or1200_monitor.v
266	First import.	lampret	8303d 20h	/or1k_old/trunk/mp3/bench/verilog/or1200_monitor.v