URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dc_top.v] - Rev 1782

Rev	Log message	Author	Age	Path
1782		root	5527d 11h	/or1k_old/trunk/or1200/rtl/verilog/or1200_dc_top.v
1765		root	5638d 03h	/or1k_old/trunk/or1200/rtl/verilog/or1200_dc_top.v
1267	Merged branch_qmem into main tree.	lampret	7438d 18h	/or1k_old/trunk/or1200/rtl/verilog/or1200_dc_top.v
1200	mbist signals updated according to newest convention	markom	7609d 18h	/or1k_old/trunk/or1200/rtl/verilog/or1200_dc_top.v
1063	Added BIST scan. Special VS RAMs need to be used to implement BIST.	lampret	7974d 06h	/or1k_old/trunk/or1200/rtl/verilog/or1200_dc_top.v
977	Added store buffer.	lampret	8034d 06h	/or1k_old/trunk/or1200/rtl/verilog/or1200_dc_top.v
660	Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.	lampret	8222d 22h	/or1k_old/trunk/or1200/rtl/verilog/or1200_dc_top.v
617	Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.	lampret	8237d 01h	/or1k_old/trunk/or1200/rtl/verilog/or1200_dc_top.v
562	Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.	lampret	8250d 20h	/or1k_old/trunk/or1200/rtl/verilog/or1200_dc_top.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8261d 18h	/or1k_old/trunk/or1200/rtl/verilog/or1200_dc_top.v