URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_mem2reg.v] - Rev 1782

Rev	Log message	Author	Age	Path
1782		root	5591d 12h	/or1k_old/trunk/or1200/rtl/verilog/or1200_mem2reg.v
1765		root	5702d 04h	/or1k_old/trunk/or1200/rtl/verilog/or1200_mem2reg.v
1022	As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.	lampret	8082d 04h	/or1k_old/trunk/or1200/rtl/verilog/or1200_mem2reg.v
788	Some of the warnings fixed.	lampret	8240d 11h	/or1k_old/trunk/or1200/rtl/verilog/or1200_mem2reg.v
777	Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2	lampret	8241d 07h	/or1k_old/trunk/or1200/rtl/verilog/or1200_mem2reg.v
562	Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.	lampret	8314d 20h	/or1k_old/trunk/or1200/rtl/verilog/or1200_mem2reg.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8325d 18h	/or1k_old/trunk/or1200/rtl/verilog/or1200_mem2reg.v