URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_rfram_generic.v] - Rev 1782

Rev	Log message	Author	Age	Path
1782		root	5527d 22h	/or1k_old/trunk/or1200/rtl/verilog/or1200_rfram_generic.v
1765		root	5638d 14h	/or1k_old/trunk/or1200/rtl/verilog/or1200_rfram_generic.v
1292	GPR0 hardwired to zero.	lampret	7374d 19h	/or1k_old/trunk/or1200/rtl/verilog/or1200_rfram_generic.v
1022	As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.	lampret	8018d 14h	/or1k_old/trunk/or1200/rtl/verilog/or1200_rfram_generic.v
871	Generic flip-flop based memory macro for register file.	lampret	8105d 20h	/or1k_old/trunk/or1200/rtl/verilog/or1200_rfram_generic.v