URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_1024x32_bw.v] - Rev 1782

Rev	Log message	Author	Age	Path
1782		root	5527d 22h	/or1k_old/trunk/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
1765		root	5638d 14h	/or1k_old/trunk/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
1582	Added support for RAMB16 Xilinx4/Spartan3 primitives	jcastillo	6877d 01h	/or1k_old/trunk/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
1291	Changed behavior of the simulation generic models	lampret	7374d 19h	/or1k_old/trunk/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
1200	mbist signals updated according to newest convention	markom	7610d 05h	/or1k_old/trunk/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
1188	Added support for rams with byte write access.	simons	7661d 04h	/or1k_old/trunk/or1200/rtl/verilog/or1200_spram_1024x32_bw.v