URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_32x24.v] - Rev 1782

Rev	Log message	Author	Age	Path
1782		root	5527d 11h	/or1k_old/trunk/or1200/rtl/verilog/or1200_spram_32x24.v
1765		root	5638d 03h	/or1k_old/trunk/or1200/rtl/verilog/or1200_spram_32x24.v
1582	Added support for RAMB16 Xilinx4/Spartan3 primitives	jcastillo	6876d 15h	/or1k_old/trunk/or1200/rtl/verilog/or1200_spram_32x24.v
1291	Changed behavior of the simulation generic models	lampret	7374d 08h	/or1k_old/trunk/or1200/rtl/verilog/or1200_spram_32x24.v
1273	Add support for 512B instruction cache.	simont	7435d 15h	/or1k_old/trunk/or1200/rtl/verilog/or1200_spram_32x24.v