URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_512x20.v] - Rev 1782

Rev	Log message	Author	Age	Path
1782		root	5591d 12h	/or1k_old/trunk/or1200/rtl/verilog/or1200_spram_512x20.v
1765		root	5702d 04h	/or1k_old/trunk/or1200/rtl/verilog/or1200_spram_512x20.v
1582	Added support for RAMB16 Xilinx4/Spartan3 primitives	jcastillo	6940d 15h	/or1k_old/trunk/or1200/rtl/verilog/or1200_spram_512x20.v
1291	Changed behavior of the simulation generic models	lampret	7438d 08h	/or1k_old/trunk/or1200/rtl/verilog/or1200_spram_512x20.v
1267	Merged branch_qmem into main tree.	lampret	7502d 18h	/or1k_old/trunk/or1200/rtl/verilog/or1200_spram_512x20.v
1200	mbist signals updated according to newest convention	markom	7673d 18h	/or1k_old/trunk/or1200/rtl/verilog/or1200_spram_512x20.v
1184	Scan signals mess fixed.	simons	7732d 10h	/or1k_old/trunk/or1200/rtl/verilog/or1200_spram_512x20.v
1179	BIST interface added for Artisan memory instances.	simons	7740d 13h	/or1k_old/trunk/or1200/rtl/verilog/or1200_spram_512x20.v
1129	Added Altera LPM RAMs. Changed generic RAM output when OE inactive.	lampret	7867d 01h	/or1k_old/trunk/or1200/rtl/verilog/or1200_spram_512x20.v
1063	Added BIST scan. Special VS RAMs need to be used to implement BIST.	lampret	8038d 06h	/or1k_old/trunk/or1200/rtl/verilog/or1200_spram_512x20.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8325d 18h	/or1k_old/trunk/or1200/rtl/verilog/or1200_spram_512x20.v