URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_tpram_32x32.v] - Rev 1782

Rev	Log message	Author	Age	Path
1782		root	5527d 22h	/or1k_old/trunk/or1200/rtl/verilog/or1200_tpram_32x32.v
1765		root	5638d 14h	/or1k_old/trunk/or1200/rtl/verilog/or1200_tpram_32x32.v
1582	Added support for RAMB16 Xilinx4/Spartan3 primitives	jcastillo	6877d 01h	/or1k_old/trunk/or1200/rtl/verilog/or1200_tpram_32x32.v
1291	Changed behavior of the simulation generic models	lampret	7374d 19h	/or1k_old/trunk/or1200/rtl/verilog/or1200_tpram_32x32.v
1267	Merged branch_qmem into main tree.	lampret	7439d 04h	/or1k_old/trunk/or1200/rtl/verilog/or1200_tpram_32x32.v
1129	Added Altera LPM RAMs. Changed generic RAM output when OE inactive.	lampret	7803d 11h	/or1k_old/trunk/or1200/rtl/verilog/or1200_tpram_32x32.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8262d 05h	/or1k_old/trunk/or1200/rtl/verilog/or1200_tpram_32x32.v