URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_tt.v] - Rev 1782

Rev	Log message	Author	Age	Path
1782		root	5497d 07h	/or1k_old/trunk/or1200/rtl/verilog/or1200_tt.v
1765		root	5607d 23h	/or1k_old/trunk/or1200/rtl/verilog/or1200_tt.v
1293	Non-functional changes. Coding style fixes.	lampret	7344d 03h	/or1k_old/trunk/or1200/rtl/verilog/or1200_tt.v
788	Some of the warnings fixed.	lampret	8146d 06h	/or1k_old/trunk/or1200/rtl/verilog/or1200_tt.v
663	No longer using async rst as sync reset for the counter.	lampret	8191d 20h	/or1k_old/trunk/or1200/rtl/verilog/or1200_tt.v
617	Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.	lampret	8206d 21h	/or1k_old/trunk/or1200/rtl/verilog/or1200_tt.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8231d 14h	/or1k_old/trunk/or1200/rtl/verilog/or1200_tt.v