URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [xsv_fpga_top.v] - Rev 1782

Rev	Log message	Author	Age	Path
1782		root	5509d 21h	/or1k_old/trunk/orp/orp_soc/rtl/verilog/xsv_fpga_top.v
1765		root	5620d 13h	/or1k_old/trunk/orp/orp_soc/rtl/verilog/xsv_fpga_top.v
1268	Merged branch_qmem into main tree.	lampret	7421d 03h	/or1k_old/trunk/orp/orp_soc/rtl/verilog/xsv_fpga_top.v
1192	disabled 'bench_defines.v' during synthesis + added define to specify usage of flash instruction address	dries	7627d 05h	/or1k_old/trunk/orp/orp_soc/rtl/verilog/xsv_fpga_top.v
1141	WB = 1/2 RISC clock test code enabled.	lampret	7784d 15h	/or1k_old/trunk/orp/orp_soc/rtl/verilog/xsv_fpga_top.v
1133	Adding OR1200_CLMODE_1TO2 test code.	lampret	7785d 11h	/or1k_old/trunk/orp/orp_soc/rtl/verilog/xsv_fpga_top.v
947	rty_i are unused - tied to zero.	lampret	8023d 06h	/or1k_old/trunk/orp/orp_soc/rtl/verilog/xsv_fpga_top.v
797	Changed hardcoded address for fake MC to use a define.	lampret	8158d 15h	/or1k_old/trunk/orp/orp_soc/rtl/verilog/xsv_fpga_top.v
792	Fixed port names that changed.	lampret	8158d 20h	/or1k_old/trunk/orp/orp_soc/rtl/verilog/xsv_fpga_top.v
789	Added response from memory controller (addr 0x60000000)	lampret	8158d 20h	/or1k_old/trunk/orp/orp_soc/rtl/verilog/xsv_fpga_top.v
752	Fixed some typos	lampret	8166d 18h	/or1k_old/trunk/orp/orp_soc/rtl/verilog/xsv_fpga_top.v
746	First import of the "new" XESS XSV environment.	lampret	8166d 19h	/or1k_old/trunk/orp/orp_soc/rtl/verilog/xsv_fpga_top.v