URL https://opencores.org/ocsvn/pci/pci/trunk

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[/] [pci/] [tags/] [asyst_3/] [rtl/] [verilog/] [pci_io_mux.v] - Rev 154

Rev	Log message	Author	Age	Path
154	New directory structure.	root	5594d 00h	/pci/tags/asyst_3/rtl/verilog/pci_io_mux.v
134	This commit was manufactured by cvs2svn to create tag 'asyst_3'.		7501d 22h	/pci/tags/asyst_3/rtl/verilog/pci_io_mux.v
132	Compact PCI Hot Swap support added. New testcases added. Specification updated. Test application changed to support WB B3 cycles.	mihad	7501d 22h	/pci/tags/asyst_3/rtl/verilog/pci_io_mux.v
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7827d 16h	/pci/tags/asyst_3/rtl/verilog/pci_io_mux.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8187d 17h	/pci/tags/asyst_3/rtl/verilog/pci_io_mux.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8307d 01h	/pci/tags/asyst_3/rtl/verilog/pci_io_mux.v
2	New project directory structure	mihad	8309d 17h	/pci/tags/asyst_3/rtl/verilog/pci_io_mux.v