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[/] [pci/] [tags/] [asyst_3/] [rtl/] [verilog/] [pci_user_constants.v] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5594d 00h /pci/tags/asyst_3/rtl/verilog/pci_user_constants.v
134 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7501d 22h /pci/tags/asyst_3/rtl/verilog/pci_user_constants.v
132 Compact PCI Hot Swap support added.
New testcases added.
Specification updated.
Test application changed to support WB B3 cycles.		 mihad 7501d 22h /pci/tags/asyst_3/rtl/verilog/pci_user_constants.v
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7639d 15h /pci/tags/asyst_3/rtl/verilog/pci_user_constants.v
86 Entered the option to disable no response counter in wb master. mihad 7781d 17h /pci/tags/asyst_3/rtl/verilog/pci_user_constants.v
79 Updated. mihad 7827d 16h /pci/tags/asyst_3/rtl/verilog/pci_user_constants.v
78 Old files with wrong names removed. mihad 7827d 16h /pci/tags/asyst_3/rtl/verilog/pci_user_constants.v
73 Bug fixes, testcases added. mihad 7833d 17h /pci/tags/asyst_3/rtl/verilog/pci_user_constants.v
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7946d 15h /pci/tags/asyst_3/rtl/verilog/pci_user_constants.v
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7994d 22h /pci/tags/asyst_3/rtl/verilog/pci_user_constants.v
33 Added some testcases, removed un-needed fifo signals mihad 8155d 21h /pci/tags/asyst_3/rtl/verilog/pci_user_constants.v
18 *** empty log message *** mihad 8187d 18h /pci/tags/asyst_3/rtl/verilog/pci_user_constants.v

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