URL https://opencores.org/ocsvn/pci/pci/trunk

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[/] [pci/] [tags/] [rel_10/] [bench/] [verilog/] [wb_master32.v] - Rev 154

Rev	Log message	Author	Age	Path
154	New directory structure.	root	5586d 21h	/pci/tags/rel_10/bench/verilog/wb_master32.v
125	This commit was manufactured by cvs2svn to create tag 'rel_10'.		7550d 20h	/pci/tags/rel_10/bench/verilog/wb_master32.v
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7632d 11h	/pci/tags/rel_10/bench/verilog/wb_master32.v
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7637d 21h	/pci/tags/rel_10/bench/verilog/wb_master32.v
92	Update!	mihad	7685d 03h	/pci/tags/rel_10/bench/verilog/wb_master32.v
15	Initial testbench import. Still under development	mihad	8180d 15h	/pci/tags/rel_10/bench/verilog/wb_master32.v