URL https://opencores.org/ocsvn/pci/pci/trunk

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[/] [pci/] [tags/] [rel_10/] [rtl/] [verilog/] [bus_commands.v] - Rev 154

Rev	Log message	Author	Age	Path
154	New directory structure.	root	5578d 04h	/pci/tags/rel_10/rtl/verilog/bus_commands.v
125	This commit was manufactured by cvs2svn to create tag 'rel_10'.		7542d 03h	/pci/tags/rel_10/rtl/verilog/bus_commands.v
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7969d 23h	/pci/tags/rel_10/rtl/verilog/bus_commands.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8171d 21h	/pci/tags/rel_10/rtl/verilog/bus_commands.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8291d 04h	/pci/tags/rel_10/rtl/verilog/bus_commands.v
2	New project directory structure	mihad	8293d 21h	/pci/tags/rel_10/rtl/verilog/bus_commands.v