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[/] [pci/] [tags/] [rel_10/] [rtl/] [verilog/] [pci_sync_module.v] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5578d 06h /pci/tags/rel_10/rtl/verilog/pci_sync_module.v
125 This commit was manufactured by cvs2svn to create tag 'rel_10'. 7542d 05h /pci/tags/rel_10/rtl/verilog/pci_sync_module.v
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7613d 01h /pci/tags/rel_10/rtl/verilog/pci_sync_module.v
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.
mihad 7754d 01h /pci/tags/rel_10/rtl/verilog/pci_sync_module.v
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7811d 22h /pci/tags/rel_10/rtl/verilog/pci_sync_module.v

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