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[/] [pci/] [tags/] [rel_10/] [rtl/] [verilog/] [pci_target32_interface.v] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5578d 06h /pci/tags/rel_10/rtl/verilog/pci_target32_interface.v
125 This commit was manufactured by cvs2svn to create tag 'rel_10'. 7542d 05h /pci/tags/rel_10/rtl/verilog/pci_target32_interface.v
116 Corrected bug when writing to FIFO (now it is registered). tadejm 7605d 18h /pci/tags/rel_10/rtl/verilog/pci_target32_interface.v
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7618d 22h /pci/tags/rel_10/rtl/verilog/pci_target32_interface.v
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7811d 22h /pci/tags/rel_10/rtl/verilog/pci_target32_interface.v
73 Bug fixes, testcases added. mihad 7817d 23h /pci/tags/rel_10/rtl/verilog/pci_target32_interface.v
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7970d 01h /pci/tags/rel_10/rtl/verilog/pci_target32_interface.v
26 Modified testbench and fixed some bugs mihad 8153d 22h /pci/tags/rel_10/rtl/verilog/pci_target32_interface.v
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8171d 23h /pci/tags/rel_10/rtl/verilog/pci_target32_interface.v
6 Updated all files with inclusion of timescale file for simulation purposes. mihad 8291d 07h /pci/tags/rel_10/rtl/verilog/pci_target32_interface.v
2 New project directory structure mihad 8293d 23h /pci/tags/rel_10/rtl/verilog/pci_target32_interface.v

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