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[/] [pci/] [tags/] [rel_10/] [rtl/] [verilog/] [pci_target_unit.v] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5585d 15h /pci/tags/rel_10/rtl/verilog/pci_target_unit.v
125 This commit was manufactured by cvs2svn to create tag 'rel_10'. 7549d 13h /pci/tags/rel_10/rtl/verilog/pci_target_unit.v
122 mbist signals updated according to newest convention markom 7556d 14h /pci/tags/rel_10/rtl/verilog/pci_target_unit.v
116 Corrected bug when writing to FIFO (now it is registered). tadejm 7613d 02h /pci/tags/rel_10/rtl/verilog/pci_target_unit.v
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7626d 06h /pci/tags/rel_10/rtl/verilog/pci_target_unit.v
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7819d 06h /pci/tags/rel_10/rtl/verilog/pci_target_unit.v
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7920d 19h /pci/tags/rel_10/rtl/verilog/pci_target_unit.v
67 Changed BIST signals for RAMs. tadejm 7921d 00h /pci/tags/rel_10/rtl/verilog/pci_target_unit.v
63 Added additional testcase and changed rst name in BIST to trst mihad 7927d 13h /pci/tags/rel_10/rtl/verilog/pci_target_unit.v
62 Added BIST signals for RAMs. mihad 7930d 06h /pci/tags/rel_10/rtl/verilog/pci_target_unit.v
58 Removed all logic from asynchronous reset network mihad 7943d 07h /pci/tags/rel_10/rtl/verilog/pci_target_unit.v
33 Added some testcases, removed un-needed fifo signals mihad 8147d 11h /pci/tags/rel_10/rtl/verilog/pci_target_unit.v
26 Modified testbench and fixed some bugs mihad 8161d 06h /pci/tags/rel_10/rtl/verilog/pci_target_unit.v
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8179d 08h /pci/tags/rel_10/rtl/verilog/pci_target_unit.v
6 Updated all files with inclusion of timescale file for simulation purposes. mihad 8298d 15h /pci/tags/rel_10/rtl/verilog/pci_target_unit.v
2 New project directory structure mihad 8301d 07h /pci/tags/rel_10/rtl/verilog/pci_target_unit.v

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