URL https://opencores.org/ocsvn/pci/pci/trunk

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[/] [pci/] [tags/] [rel_10/] [rtl/] [verilog/] [pci_user_constants.v] - Rev 154

Rev	Log message	Author	Age	Path
154	New directory structure.	root	5587d 04h	/pci/tags/rel_10/rtl/verilog/pci_user_constants.v
125	This commit was manufactured by cvs2svn to create tag 'rel_10'.		7551d 03h	/pci/tags/rel_10/rtl/verilog/pci_user_constants.v
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7632d 18h	/pci/tags/rel_10/rtl/verilog/pci_user_constants.v
86	Entered the option to disable no response counter in wb master.	mihad	7774d 21h	/pci/tags/rel_10/rtl/verilog/pci_user_constants.v
79	Updated.	mihad	7820d 19h	/pci/tags/rel_10/rtl/verilog/pci_user_constants.v
78	Old files with wrong names removed.	mihad	7820d 20h	/pci/tags/rel_10/rtl/verilog/pci_user_constants.v
73	Bug fixes, testcases added.	mihad	7826d 20h	/pci/tags/rel_10/rtl/verilog/pci_user_constants.v
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7939d 19h	/pci/tags/rel_10/rtl/verilog/pci_user_constants.v
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7988d 01h	/pci/tags/rel_10/rtl/verilog/pci_user_constants.v
33	Added some testcases, removed un-needed fifo signals	mihad	8149d 01h	/pci/tags/rel_10/rtl/verilog/pci_user_constants.v
18	* empty log message *	mihad	8180d 22h	/pci/tags/rel_10/rtl/verilog/pci_user_constants.v