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[/] [pci/] [tags/] [rel_10/] [rtl/] [verilog/] [pci_wbw_fifo_control.v] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5585d 11h /pci/tags/rel_10/rtl/verilog/pci_wbw_fifo_control.v
125 This commit was manufactured by cvs2svn to create tag 'rel_10'. 7549d 10h /pci/tags/rel_10/rtl/verilog/pci_wbw_fifo_control.v
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7620d 06h /pci/tags/rel_10/rtl/verilog/pci_wbw_fifo_control.v
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.
mihad 7636d 11h /pci/tags/rel_10/rtl/verilog/pci_wbw_fifo_control.v
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.
mihad 7761d 06h /pci/tags/rel_10/rtl/verilog/pci_wbw_fifo_control.v
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7819d 02h /pci/tags/rel_10/rtl/verilog/pci_wbw_fifo_control.v

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