URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_10/] [rtl/] [verilog/] [pci_wbw_fifo_control.v] - Rev 154

Rev	Log message	Author	Age	Path
154	New directory structure.	root	5589d 12h	/pci/tags/rel_10/rtl/verilog/pci_wbw_fifo_control.v
125	This commit was manufactured by cvs2svn to create tag 'rel_10'.		7553d 11h	/pci/tags/rel_10/rtl/verilog/pci_wbw_fifo_control.v
111	synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.	simons	7624d 07h	/pci/tags/rel_10/rtl/verilog/pci_wbw_fifo_control.v
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7640d 12h	/pci/tags/rel_10/rtl/verilog/pci_wbw_fifo_control.v
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7765d 07h	/pci/tags/rel_10/rtl/verilog/pci_wbw_fifo_control.v
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7823d 03h	/pci/tags/rel_10/rtl/verilog/pci_wbw_fifo_control.v