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[/] [pci/] [tags/] [rel_10/] [rtl/] [verilog/] [top.v] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5578d 04h /pci/tags/rel_10/rtl/verilog/top.v
125 This commit was manufactured by cvs2svn to create tag 'rel_10'. 7542d 02h /pci/tags/rel_10/rtl/verilog/top.v
122 mbist signals updated according to newest convention markom 7549d 03h /pci/tags/rel_10/rtl/verilog/top.v
115 Added signals for WB Master B3. tadejm 7605d 15h /pci/tags/rel_10/rtl/verilog/top.v
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7623d 18h /pci/tags/rel_10/rtl/verilog/top.v
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7811d 19h /pci/tags/rel_10/rtl/verilog/top.v
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7913d 08h /pci/tags/rel_10/rtl/verilog/top.v
67 Changed BIST signals for RAMs. tadejm 7913d 13h /pci/tags/rel_10/rtl/verilog/top.v
63 Added additional testcase and changed rst name in BIST to trst mihad 7920d 02h /pci/tags/rel_10/rtl/verilog/top.v
62 Added BIST signals for RAMs. mihad 7922d 19h /pci/tags/rel_10/rtl/verilog/top.v
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8124d 04h /pci/tags/rel_10/rtl/verilog/top.v
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8171d 21h /pci/tags/rel_10/rtl/verilog/top.v
6 Updated all files with inclusion of timescale file for simulation purposes. mihad 8291d 04h /pci/tags/rel_10/rtl/verilog/top.v
2 New project directory structure mihad 8293d 20h /pci/tags/rel_10/rtl/verilog/top.v

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