OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_11/] [rtl/] [verilog/] [pci_user_constants.v] - Rev 154

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
154 New directory structure. root 5577d 18h /pci/tags/rel_11/rtl/verilog/pci_user_constants.v
127 This commit was manufactured by cvs2svn to create tag 'rel_11'. 7503d 10h /pci/tags/rel_11/rtl/verilog/pci_user_constants.v
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.
mihad 7623d 09h /pci/tags/rel_11/rtl/verilog/pci_user_constants.v
86 Entered the option to disable no response counter in wb master. mihad 7765d 11h /pci/tags/rel_11/rtl/verilog/pci_user_constants.v
79 Updated. mihad 7811d 10h /pci/tags/rel_11/rtl/verilog/pci_user_constants.v
78 Old files with wrong names removed. mihad 7811d 10h /pci/tags/rel_11/rtl/verilog/pci_user_constants.v
73 Bug fixes, testcases added. mihad 7817d 11h /pci/tags/rel_11/rtl/verilog/pci_user_constants.v
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7930d 09h /pci/tags/rel_11/rtl/verilog/pci_user_constants.v
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7978d 16h /pci/tags/rel_11/rtl/verilog/pci_user_constants.v
33 Added some testcases, removed un-needed fifo signals mihad 8139d 15h /pci/tags/rel_11/rtl/verilog/pci_user_constants.v
18 *** empty log message *** mihad 8171d 12h /pci/tags/rel_11/rtl/verilog/pci_user_constants.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.