URL https://opencores.org/ocsvn/pci/pci/trunk

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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [conf_space.v] - Rev 154

Rev	Log message	Author	Age	Path
154	New directory structure.	root	5581d 21h	/pci/tags/rel_3/rtl/verilog/conf_space.v
74	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7821d 14h	/pci/tags/rel_3/rtl/verilog/conf_space.v
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7982d 19h	/pci/tags/rel_3/rtl/verilog/conf_space.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8175d 14h	/pci/tags/rel_3/rtl/verilog/conf_space.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8294d 21h	/pci/tags/rel_3/rtl/verilog/conf_space.v
2	New project directory structure	mihad	8297d 14h	/pci/tags/rel_3/rtl/verilog/conf_space.v