URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [pci_target32_sm.v] - Rev 154

Rev	Log message	Author	Age	Path
154	New directory structure.	root	5580d 14h	/pci/tags/rel_3/rtl/verilog/pci_target32_sm.v
74	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7820d 07h	/pci/tags/rel_3/rtl/verilog/pci_target32_sm.v
73	Bug fixes, testcases added.	mihad	7820d 07h	/pci/tags/rel_3/rtl/verilog/pci_target32_sm.v
56	Number of state bits define was removed	mihad	7939d 03h	/pci/tags/rel_3/rtl/verilog/pci_target32_sm.v
55	Changed state machine encoding to true one-hot	mihad	7939d 04h	/pci/tags/rel_3/rtl/verilog/pci_target32_sm.v
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7972d 14h	/pci/tags/rel_3/rtl/verilog/pci_target32_sm.v
26	Modified testbench and fixed some bugs	mihad	8156d 06h	/pci/tags/rel_3/rtl/verilog/pci_target32_sm.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8174d 07h	/pci/tags/rel_3/rtl/verilog/pci_target32_sm.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8293d 14h	/pci/tags/rel_3/rtl/verilog/pci_target32_sm.v
2	New project directory structure	mihad	8296d 07h	/pci/tags/rel_3/rtl/verilog/pci_target32_sm.v