URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [pci_target_unit.v] - Rev 154

Rev	Log message	Author	Age	Path
154	New directory structure.	root	5580d 01h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v
74	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7819d 18h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7915d 06h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v
67	Changed BIST signals for RAMs.	tadejm	7915d 11h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v
63	Added additional testcase and changed rst name in BIST to trst	mihad	7922d 00h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v
62	Added BIST signals for RAMs.	mihad	7924d 16h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v
58	Removed all logic from asynchronous reset network	mihad	7937d 18h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v
33	Added some testcases, removed un-needed fifo signals	mihad	8141d 22h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v
26	Modified testbench and fixed some bugs	mihad	8155d 17h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8173d 18h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8293d 01h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v
2	New project directory structure	mihad	8295d 18h	/pci/tags/rel_3/rtl/verilog/pci_target_unit.v