URL https://opencores.org/ocsvn/pci/pci/trunk

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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [pciw_pcir_fifos.v] - Rev 154

Rev	Log message	Author	Age	Path
154	New directory structure.	root	5576d 10h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
74	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7816d 02h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7911d 15h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
67	Changed BIST signals for RAMs.	tadejm	7911d 20h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
63	Added additional testcase and changed rst name in BIST to trst	mihad	7918d 08h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
62	Added BIST signals for RAMs.	mihad	7921d 01h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7929d 02h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
58	Removed all logic from asynchronous reset network	mihad	7934d 03h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
33	Added some testcases, removed un-needed fifo signals	mihad	8138d 07h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8170d 03h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8289d 10h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v
2	New project directory structure	mihad	8292d 03h	/pci/tags/rel_3/rtl/verilog/pciw_pcir_fifos.v