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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [top.v] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5580d 02h /pci/tags/rel_3/rtl/verilog/top.v
74 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7819d 18h /pci/tags/rel_3/rtl/verilog/top.v
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7915d 07h /pci/tags/rel_3/rtl/verilog/top.v
67 Changed BIST signals for RAMs. tadejm 7915d 12h /pci/tags/rel_3/rtl/verilog/top.v
63 Added additional testcase and changed rst name in BIST to trst mihad 7922d 00h /pci/tags/rel_3/rtl/verilog/top.v
62 Added BIST signals for RAMs. mihad 7924d 17h /pci/tags/rel_3/rtl/verilog/top.v
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8126d 03h /pci/tags/rel_3/rtl/verilog/top.v
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8173d 19h /pci/tags/rel_3/rtl/verilog/top.v
6 Updated all files with inclusion of timescale file for simulation purposes. mihad 8293d 02h /pci/tags/rel_3/rtl/verilog/top.v
2 New project directory structure mihad 8295d 19h /pci/tags/rel_3/rtl/verilog/top.v

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