URL https://opencores.org/ocsvn/pci/pci/trunk

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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [wb_master.v] - Rev 154

Rev	Log message	Author	Age	Path
154	New directory structure.	root	5582d 11h	/pci/tags/rel_3/rtl/verilog/wb_master.v
74	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7822d 03h	/pci/tags/rel_3/rtl/verilog/wb_master.v
72	* empty log message *	mihad	7869d 07h	/pci/tags/rel_3/rtl/verilog/wb_master.v
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7924d 05h	/pci/tags/rel_3/rtl/verilog/wb_master.v
33	Added some testcases, removed un-needed fifo signals	mihad	8144d 07h	/pci/tags/rel_3/rtl/verilog/wb_master.v
26	Modified testbench and fixed some bugs	mihad	8158d 02h	/pci/tags/rel_3/rtl/verilog/wb_master.v
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8176d 04h	/pci/tags/rel_3/rtl/verilog/wb_master.v
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8295d 11h	/pci/tags/rel_3/rtl/verilog/wb_master.v
2	New project directory structure	mihad	8298d 03h	/pci/tags/rel_3/rtl/verilog/wb_master.v