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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [wb_slave_unit.v] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5580d 14h /pci/tags/rel_3/rtl/verilog/wb_slave_unit.v
74 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7820d 06h /pci/tags/rel_3/rtl/verilog/wb_slave_unit.v
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7915d 19h /pci/tags/rel_3/rtl/verilog/wb_slave_unit.v
67 Changed BIST signals for RAMs. tadejm 7916d 00h /pci/tags/rel_3/rtl/verilog/wb_slave_unit.v
63 Added additional testcase and changed rst name in BIST to trst mihad 7922d 12h /pci/tags/rel_3/rtl/verilog/wb_slave_unit.v
62 Added BIST signals for RAMs. mihad 7925d 05h /pci/tags/rel_3/rtl/verilog/wb_slave_unit.v
58 Removed all logic from asynchronous reset network mihad 7938d 07h /pci/tags/rel_3/rtl/verilog/wb_slave_unit.v
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8174d 07h /pci/tags/rel_3/rtl/verilog/wb_slave_unit.v
6 Updated all files with inclusion of timescale file for simulation purposes. mihad 8293d 14h /pci/tags/rel_3/rtl/verilog/wb_slave_unit.v
2 New project directory structure mihad 8296d 07h /pci/tags/rel_3/rtl/verilog/wb_slave_unit.v

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