OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [wbr_fifo_control.v] - Rev 154

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
154 New directory structure. root 5580d 06h /pci/tags/rel_3/rtl/verilog/wbr_fifo_control.v
74 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7819d 23h /pci/tags/rel_3/rtl/verilog/wbr_fifo_control.v
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.
mihad 7874d 18h /pci/tags/rel_3/rtl/verilog/wbr_fifo_control.v
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7932d 23h /pci/tags/rel_3/rtl/verilog/wbr_fifo_control.v
58 Removed all logic from asynchronous reset network mihad 7937d 23h /pci/tags/rel_3/rtl/verilog/wbr_fifo_control.v
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8173d 23h /pci/tags/rel_3/rtl/verilog/wbr_fifo_control.v
6 Updated all files with inclusion of timescale file for simulation purposes. mihad 8293d 07h /pci/tags/rel_3/rtl/verilog/wbr_fifo_control.v
2 New project directory structure mihad 8295d 23h /pci/tags/rel_3/rtl/verilog/wbr_fifo_control.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.