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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [wbw_fifo_control.v] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5576d 08h /pci/tags/rel_3/rtl/verilog/wbw_fifo_control.v
74 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7816d 01h /pci/tags/rel_3/rtl/verilog/wbw_fifo_control.v
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.
mihad 7870d 20h /pci/tags/rel_3/rtl/verilog/wbw_fifo_control.v
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7929d 01h /pci/tags/rel_3/rtl/verilog/wbw_fifo_control.v
58 Removed all logic from asynchronous reset network mihad 7934d 01h /pci/tags/rel_3/rtl/verilog/wbw_fifo_control.v
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8170d 01h /pci/tags/rel_3/rtl/verilog/wbw_fifo_control.v
6 Updated all files with inclusion of timescale file for simulation purposes. mihad 8289d 09h /pci/tags/rel_3/rtl/verilog/wbw_fifo_control.v
2 New project directory structure mihad 8292d 01h /pci/tags/rel_3/rtl/verilog/wbw_fifo_control.v

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