URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_4/] [bench/] [verilog/] [pci_testbench_defines.v] - Rev 154

Rev	Log message	Author	Age	Path
154	New directory structure.	root	5574d 16h	/pci/tags/rel_4/bench/verilog/pci_testbench_defines.v
80	This commit was manufactured by cvs2svn to create tag 'rel_4'.		7808d 08h	/pci/tags/rel_4/bench/verilog/pci_testbench_defines.v
73	Bug fixes, testcases added.	mihad	7814d 09h	/pci/tags/rel_4/bench/verilog/pci_testbench_defines.v
69	Changed BIST signal names etc..	mihad	7906d 12h	/pci/tags/rel_4/bench/verilog/pci_testbench_defines.v
66	Changed empty status generation in pciw_fifo_control.v	mihad	7913d 12h	/pci/tags/rel_4/bench/verilog/pci_testbench_defines.v
63	Added additional testcase and changed rst name in BIST to trst	mihad	7916d 15h	/pci/tags/rel_4/bench/verilog/pci_testbench_defines.v
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7966d 08h	/pci/tags/rel_4/bench/verilog/pci_testbench_defines.v
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7975d 14h	/pci/tags/rel_4/bench/verilog/pci_testbench_defines.v
26	Modified testbench and fixed some bugs	mihad	8150d 08h	/pci/tags/rel_4/bench/verilog/pci_testbench_defines.v
15	Initial testbench import. Still under development	mihad	8168d 11h	/pci/tags/rel_4/bench/verilog/pci_testbench_defines.v