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[/] [pci/] [tags/] [rel_5/] [bench/] [verilog/] [pci_testbench_defines.v] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5577d 00h /pci/tags/rel_5/bench/verilog/pci_testbench_defines.v
82 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7807d 11h /pci/tags/rel_5/bench/verilog/pci_testbench_defines.v
73 Bug fixes, testcases added. mihad 7816d 17h /pci/tags/rel_5/bench/verilog/pci_testbench_defines.v
69 Changed BIST signal names etc.. mihad 7908d 20h /pci/tags/rel_5/bench/verilog/pci_testbench_defines.v
66 Changed empty status generation in pciw_fifo_control.v mihad 7915d 20h /pci/tags/rel_5/bench/verilog/pci_testbench_defines.v
63 Added additional testcase and changed rst name in BIST to trst mihad 7918d 23h /pci/tags/rel_5/bench/verilog/pci_testbench_defines.v
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7968d 16h /pci/tags/rel_5/bench/verilog/pci_testbench_defines.v
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7977d 22h /pci/tags/rel_5/bench/verilog/pci_testbench_defines.v
26 Modified testbench and fixed some bugs mihad 8152d 16h /pci/tags/rel_5/bench/verilog/pci_testbench_defines.v
15 Initial testbench import. Still under development mihad 8170d 19h /pci/tags/rel_5/bench/verilog/pci_testbench_defines.v

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